Verfahren zur vollständigen Metallisierung einer Substrat-Durchkontaktierung in einem dielektrischen Substrat sowie ein dielektrisches Substrat umfassend eine solche Durchkontaktierung

Publication: DE102024126529A1
Published: 2026-03-19
Family Size: 2
Granted: No

Patent Abstract

The present invention relates to a method for completely metallising a substrate via (2) in a dielectric substrate (1), wherein the method comprises the following steps: - forming a funnel-shaped structure (10) in the dielectric substrate (1), which structure extends from a rear side (3) to a front side (4) opposite the rear side (3) along a first direction, wherein the funnel-shaped structure (10) has a first part (11) which tapers along a first direction; - applying an electroplating start layer (20) exclusively to the rear side (3) and the first part (11); - depositing a metal layer (30) by means of an electroplating process in the funnel-shaped structure (10) in a region of a first part (11) at which a diameter is smallest, such that the funnel-shaped structure (10) is closed; and - filling the funnel-shaped structure (10) by introducing the metal layer (30) by means of the electroplating process, such that the funnel-shaped structure (10) is completely filled between the region of the first part (11) and the front side (4); and - removing the electroplating start layer (20) from the rear side (3).

Simple SummaryContent extracted with AI.

This invention describes a method for fully metallizing through-holes (vias) in dielectric substrates like glass or ceramics. The process involves creating a funnel-shaped cavity in the substrate, depositing a seed layer on selected areas, and then electroplating the cavity to completely fill it with metal (such as gold or copper). After metallization, the seed layer is removed from the backside. This results in an electrically conductive via that connects the front and back surfaces of the substrate, which is particularly useful for high-density, reliable connections in microelectronics and MEMS devices.

Use CasesContent extracted with AI.

  • Fabrication of high-performance integrated circuits using non-silicon substrates (e.g., glass, sapphire) for advanced microelectronic packaging.
  • Production of micro-electro-mechanical systems (MEMS) where dielectric substrates are needed for superior electrical or thermal properties.
  • Creation of substrates for ion traps or quantum devices requiring high-purity, chemically inert metallization (e.g., gold-filled vias).
  • High-frequency or RF circuit boards where low electrical losses and high via density are required.
  • Three-dimensional (3D) integration and packaging technologies needing dense, reliable vertical interconnections through dielectric substrates.

BenefitsContent extracted with AI.

  • Enables complete, void-free metallization of vias in challenging high aspect ratio structures, overcoming limitations of partial or conformal filling methods.
  • Supports the use of high-purity, inert metals such as gold, which reduces corrosion, improves reliability, and is suitable for sensitive applications (e.g., quantum technologies).
  • Allows for higher via density and compact substrate designs, benefiting integration and miniaturization of electronic systems.
  • Eliminates the need for complex chemical additives during electroplating, resulting in a more environmentally friendly and potentially cost-effective process.
  • Improves thermal and electrical connectivity through dielectric substrates, expanding the functional possibilities for advanced electronics and MEMS components.

Technical Classifications (CPCs)

Main Classifications

Electrical & Electronic Tech

Sub Classifications

Semiconductor & Solid-State Devices

CPC Codes

H10W20/20H10W70/095H10W70/635

Inventors & Applicants

Inventors

Friederike Giebel

Eike Iseke

Jacob Stupp

Konstantin Thronberens

Amado Bautista-salvador

Christian Joohs

Nila Krishnakumar

Christian Ospelkaus

Applicant(s)

Gottfried Wilhelm Leibniz Univ Hannover Koerperschaft Des Oeffentlichen Rechts

Phys Technische Bundesanstalt Braunschweig Und Berlin

Key Information

Publication No.

DE102024126529A1

Family ID

97215360

Publication Date

2026-03-19

Application No.

DE102024126529A

Application Date

2024-09-13

Priority Date

2024-09-13

Granted

No

Possible Cooperation

For further information please contact the transfer office.